Ahead of next week’s Flash Memory Summit, Micron this morning is announcing that their next-generation 232 layer NAND has begun shipping. The sixth generation of Micron’s 3D NAND technology, 232L is slated to offer both improved bandwidth and larger die sizes – most notably, introducing Micron’s first 1Tbit TLC NAND dies, which at this point are the densest in the industry. According to the company, the new NAND is already shipping to customers and in Crucial SSD products in limited volumes, with further volume ramping to take place later in the year.

Micron first announced their 232L NAND back in May during their Investor Day event, revealing that the NAND would be available this year, and that the company intended to ramp up production by the end of the year. And while that yield ramp is still ongoing, Micron’s Singapore fab is already capable of producing enough of the new NAND that Micron is comfortable in announcing it is shipping, albeit clearly in limited quantities.

From a technical perspective, Micron’s 232L NAND further builds upon the basic design elements Micron honed in that generation. So we’re once again looking at a string stacked design, with Micron using a pair of 116 layer decks, up from 88 layers in the previous generation. 116 layer decks, in turn, are notable as this is the first time Micron has been able to produce a single deck over 100 layers, a feat previously limited to Samsung. This in turn has allowed Micron to produce cutting-edge NAND with just two decks, something that may not be possible for much longer as companies push toward designs with over 300 total layers.

Micron’s NAND decks continue to be built with their charge-trap, CMOS under Array (CuA) architecture, which sees the bulk of the NAND’s logic placed under the NAND memory cells. Micron has long cited this as giving them an ongoing advantage in NAND density, and that’s once again on show for their 232L NAND. According to the company they’ve achieved a density of 14.6 Gbit/mm2, which is about 43% denser than their 176L NAND. And, according to Micron, anywhere between 35% to 100% denser than competing TLC products.

Micron 3D TLC NAND Flash Memory
Layers 232 176
Decks 2 (x116) 2 (x88)
Die Capacity 1 Tbit 512 Gbit
Die Size (mm2) ~70.1mm2 ~49.8mm2
Density (Gbit/mm2) 14.6 10.3
I/O Speed 2.4 MT/s
(ONFi 5.0)
1.6 MT/s
(ONFI 4.2)
Program Throughput ? ?
Planes 6 4
CuA / PuC Yes Yes

The improved density has allowed Micron to finally produce their first 1Tbit TLC die, which from a productization standpoint means that Micron can now also produce 2TB chip packages by stacking 16 of their 232L dies. This is good news for SSD capacities, which at the high-end are often limited by the number of packages that can be placed. Though it does mean that there’s a potential loss of performance at lower capacities due to a decrease parallelism from implementing fewer packages.

At the same time, Micron has also been working on the size of their chip packaging, and as a result while the larger capacity means that their die size has increased on a generational basis (we estimate ~70.1mm2 given Micron’s density figures), they’ve still shrunk their chip packaging by 28%. As a result, a single chip package is down from 12mm x 18mm (216mm2) to 11.5mm x 13.5mm (~155mm2). So for Micron’s downstream customers, the combination of the greater capacity and physically smaller packages for Micron’s NAND means that device manufacturers can cut down on the amount of space they allocate to NAND packages, or go the other direction and try to cram in even more packages into a similar amount of space.

Besides density improvements, the latest generation of Micron’s NAND is also allowing the company to upgrade their hardware to take advantage of newer I/O technologies, as well as to implement their own improvements to increase transfer speeds. The big news here is that Micron has increased the number of planes within their NAND die from 4 to 6, further improving the parallelism available within each die.  Quad (four) plane designs became common in the previous generation of NAND, and as the density of NAND grows, so too are the number of planes in order for transfer rates to keep up with these greater densities. Micron has confirmed that the planes in 232L NAND offer independent reads, though they aren’t being quite as explicit on what kind of wordline dependencies remain for writes.

This increase in parallelism, along with improved internal transfer rates, has allowed Micron to significantly improve their per-die read and write speeds. According to the company, read speeds have improved by over 75% over their 176L generation NAND, and meanwhile write speeds have outright doubled.

Coupled with this, Micron has also implemented the latest generation of ONFi on their peripheral logic. Finalized in 2021 and now rolling out in the first NAND products, ONFi increases controller-NAND transfer rates by 50%, bringing it to 2400MT/second. ONFi 5.0 also introduced a new NV-LPDDR4 signaling method, which is available with the same 2400MT/s rate but, as it’s based on LPDDR technology, consumes less power. According to Micron, they’re seeing per-bit energy transfer savings of over 30%, which makes for a significant reduction in energy consumption. Though as always with these sorts of comparisons, it’s worth noting that the bandwidth gains exceed the energy savings (50% vs. 30%), so our expectation is that overall energy consumption is going to go up for high-performance products that run at the fastest speeds supported by Micron’s 232L NAND.

As for productization, Micron is pitching 232L NAND as a full stack replacement for 176L NAND – meaning that Micron considers it suitable for everything from mobile and IoT to clients and data center products. To that end, the company is already making initial shipments to their customers, including their own Crucial subsidiary. As with past generations of Micron NAND, starting early with Crucial allows the company to get some hands-on experience in developing full-featured products with their new NAND before they roll it into their own enterprise equipment. Interestingly, however, Micron isn’t announcing any new Crucial products right now, which strongly implies that Crucial is going to begin implementing the new NAND in existing products. If that’s the case, then Crucial customers will want to pay attention to what’s going on and what revision of a drive they’re buying, as the larger 1Tb die could have performance implications for products originally designed around 512Gbit dies.

Wrapping things up, today’s announcement should be the tip of the iceberg for Micron’s 232L shipments. With volume ramping expected to continue through this end of this calendar year, Micron’s plans call for the company to significantly increase the amount of next-generation NAND they’re shipping, going well beyond these initial volumes. Ultimately, this means that products equipped with 232L NAND are going to be relatively sparse for this year, and will pick up in 2023 following the volume ramp. So while Micron’s 232L NAND is indeed shipping, from a consumer standpoint we’re likely still several months off (or more) from seeing it becoming a common fixture in SSDs and other products.

Source: Micron

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  • AMv8(1day) - Tuesday, July 26, 2022 - link

    Thanks for the write up Ryan,
    There is mention of the implied larger capacities, but without going around inspecting everyone's M.2 PCBs, I'm not sure what the current max feasible package count would be for this. Are we looking at 8TB+ options on single sided M.2? More value oriented 8TB M.2s?
    Will this be backported to their value SATA drive options? I'm sure that you could easily outstrip 3.5" HDD limits with a 20+TB 2.5" SSD. Of course pricing would reflect, but a 232L TLC/QLC/PLC SATA drive could actually pose a perf for value argument...
  • Ryan Smith - Tuesday, July 26, 2022 - link

    For high performance SSDs, most current single-sided designs are 2 NAND packages + DRAM and a controller. So Micron's 232L NAND would allow for those SSDs to be built out to 4TB capacities.

    I imagine there are some DRAMless drives out there that have worked in 4 packages on a single side, so they'd theoretically be able to go up to 8TB. But off the top of my head I don't know of any such drives.
  • BoredErica - Tuesday, August 9, 2022 - link

    Is there a reason why many 2tb versions of ssds have slightly lower qd1 randoms?
  • romrunning - Wednesday, July 27, 2022 - link

    You could get more dies on a 22110 m.2 drive, not just the regular 2280 length.
  • technoshark - Friday, July 29, 2022 - link

    Can someone explain the terminology? What constitutes a layer, deck? Does this device have 232 memory cells stacked vertically, or does it have 232 process layers (which would imply much smaller number of stacked memory cells)
  • blanarahul - Monday, August 1, 2022 - link

    Yes it was 232 cells stacked vertically.
  • Ryan Smith - Wednesday, August 3, 2022 - link

    To steal something Billy wrote a couple of years ago:

    Terminology Info: NAND companies build 'decks' of 32-116 layers of bits, and then combine decks to get a total number of layers. Building more layers in a single deck is difficult, and so combining decks gives a higher total number of layers. Typically the companies that can put more layers in a single deck are said to have a more advanced process. Most companies use two decks to reach 150+ layers, while Intel/Solidigm used 3 decks of 48 layers to reach 144 layers .

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