It’s no secret that Intel’s enterprise processor platform has been stretched in recent generations. Compared to the competition, Intel is chasing its multi-die strategy while relying on a manufacturing platform that hasn’t offered the best in the market. That being said, Intel is quoting more shipments of its latest Xeon products in December than AMD shipped in all of 2021, and the company is launching the next generation Sapphire Rapids Xeon Scalable platform later in 2022. Beyond Sapphire Rapids has been somewhat under the hood, with minor leaks here and there, but today Intel is lifting the lid on that roadmap.

State of Play Today

Currently in the market is Intel’s Ice Lake 3rd Generation Xeon Scalable platform, built on Intel’s 10nm process node with up to 40 Sunny Cove cores. The die is large, around 660 mm2, and in our benchmarks we saw a sizeable generational uplift in performance compared to the 2nd Generation Xeon offering. The response to Ice Lake Xeon has been mixed, given the competition in the market, but Intel has forged ahead by leveraging a more complete platform coupled with FPGAs, memory, storage, networking, and its unique accelerator offerings. Datacenter revenues, depending on the quarter you look at, are either up or down based on how customers are digesting their current processor inventories (as stated by CEO Pat Gelsinger).

That being said, Intel has put a large amount of effort into discussing its 4th Generation Xeon Scalable platform, Sapphire Rapids. For example, we already know that it will be using >1600 mm2 of silicon for the highest core count solutions, with four tiles connected with Intel’s embedded bridge technology. The chip will have eight 64-bit memory channels of DDR5, support for PCIe 5.0, as well as most of the CXL 1.1 specification. New matrix extensions also come into play, along with data streaming accelerators, quick assist technology, all built on the latest P-core designs currently present in the Alder Lake desktop platform, albeit optimized for datacenter use (which typically means AVX512 support and bigger caches). We already know that versions of Sapphire Rapids will be available with HBM memory, and the first customer for those chips will be the Aurora supercomputer at Argonne National Labs, coupled with the new Ponte Vecchio high-performance compute accelerator.

The launch of Sapphire Rapids is significantly later than originally envisioned several years ago, but we expect to see the hardware widely available during 2022, built on Intel 7 process node technology.

Next Generation Xeon Scalable

Looking beyond Sapphire Rapids, Intel is finally putting materials into the public to showcase what is coming up on the roadmap. After Sapphire Rapids, we will have a platform compatible Emerald Rapids Xeon Scalable product, also built on Intel 7, in 2023. Given the naming conventions, Emerald Rapids is likely to be the 5th Generation.

Emerald Rapids (EMR), as with some other platform updates, is expected to capture the low hanging fruit from the Sapphire Rapids design to improve performance, as well as updates from the manufacturing. With platform compatibility, it means Emerald will have the same support when it comes to PCIe lanes, CPU-to-CPU connectivity, DRAM, CXL, and other IO features. We’re likely to see updated accelerators too. Exactly what the silicon will look like however is still an unknown. As we’re still new in Intel’s tiled product portfolio, there’s a good chance it will be similar to Sapphire Rapids, but it could equally be something new, such as what Intel has planned for the generation after.

After Emerald Rapids is where Intel’s roadmap takes on a new highway. We’re going to see a diversification in Intel’s strategy on a number of levels.

Starting at the top is Granite Rapids (GNR), built entirely of Intel’s performance cores, on an Intel 3 process node for launch in 2024. Previously Granite Rapids had been on roadmaps as an Intel 4 node product, however, Intel has stated to us that the progression of the technology as well as the timeline of where it will come into play makes it better to put Granite on that Intel 3 node. Intel 3 is meant to be Intel’s second-generation EUV node after Intel 4, and we expect the design rules to be very similar between the two, so it’s not that much of a jump from one to the other we suspect.

Granite Rapids will be a tiled architecture, just as before, but it will also feature a bifurcated strategy in its tiles: it will have separate IO tiles and separate core tiles, rather than a unified design like Sapphire Rapids. Intel hasn’t disclosed how they will be connected, but the idea here is that the IO tile(s) can contain all the memory channels, PCIe lanes, and other functionality while the core tiles can be focused purely on performance. Yes, it sounds like what Intel’s competition is doing today, but ultimately it’s the right thing to do.

Granite Rapids will share a platform with Intel’s new product line, which starts with Sierra Forest (SRF) which is also on Intel 3. This new product line will be built from datacenter optimized E-cores, which we’re familiar with from Intel’s current Alder Lake consumer portfolio. The E-cores in Sierra Forest will be a future generation than the Gracemont E-cores we have today, but the idea here is to provide a product that focuses more on core density rather than outright core performance. This allows them to run at lower voltages and parallelize, assuming the memory bandwidth and interconnect can keep up.

Sierra Forest will be using the same IO die as Granite Rapids. The two will share a platform – we assume in this instance this means they will be socket compatible – so we expect to see the same DDR and PCIe configurations for both. If Intel’s numbering scheme continues, GNR and SRF will be Xeon Scalable 6th Generation products. Intel stated to us in our briefing that the product portfolio currently offered by Ice Lake Xeon products will be covered and extended by a mix of GNR and SRF Xeons based on customer requirements. Both GNR and SRF are expected to have full global availability when launched.

The E-core Sierra Forest focused on core density will end up being compared to AMD’s equivalent, which for Zen4c will be called Bergamo – AMD might have a Zen5 equivalent when SRF comes to market.

I asked Intel whether the move to GNR+SRF on one unified platform means the generation after will be a unique platform, or whether it will retain the two-generation retention that customers like. I was told that it would be ideal to maintain platform compatibility across the generations, although as these are planned out, it depends on timing and where new technologies need to be integrated. The earliest industry estimates (beyond CPU) for PCIe 6.0 are in the 2026 timeframe, and DDR6 is more like 2029, so unless there are more memory channels to add it’s likely we’re going to see parity between 6th and 7th Gen Xeon.

My other question to Intel was about Hybrid CPU designs – if Intel was now going to make P-core tiles and E-core tiles, what’s stopping a combined product with both? Intel stated that their customers prefer uni-core designs in this market as the needs from customer to customer differ. If one customer prefers an 80/20 split on P-cores to E-cores, there’s another customer that prefers a 20/80 split. Having a wide array of products for each different ratio doesn’t make sense, and customers already investigating this are finding out that the software works better with a homogeneous arrangement, instead split at the system level, rather than the socket level. So we’re not likely to see hybrid Xeons any time soon. (Ian: Which is a good thing.)

I did ask about the unified IO die - giving the same P-core only and E-core only Xeons the same number of memory channels and I/O lanes might not be optimal for either scenario. Intel didn’t really have a good answer here, aside from the fact that building them both into the same platform helped customers synergize non-returnable development costs across both CPUs, regardless of the one they used. I didn’t ask at the time, but we could see the door open to more Xeon-D-like scenarios with different IO configurations for smaller deployments, but we’re talking products that are 2-3+ years away at this point.

Xeon Scalable Generations
Date AnandTech Codename Abbr. Max
Cores
Node Socket
Q3 2017 1st Skylake SKL 28 14nm LGA 3647
Q2 2019 2nd Cascade Lake CXL 28 14nm LGA 3647
Q2 2020 3rd Cooper Lake CPL 28 14nm LGA 4189
Q2 2021 Ice Lake ICL 40 10nm LGA 4189
2022 4th Sapphire Rapids SPR * Intel 7 LGA 4677
2023 5th Emerald Rapids EMR ? Intel 7 **
2024 6th Granite Rapids GNR ? Intel 3 ?
Sierra Forest SRF ? Intel 3
>2024 7th Next-Gen P ? ? ? ?
Next-Gen E
* Estimate is 56 cores
** Estimate is LGA4677

For both Granite Rapids and Sierra Forest, Intel is already working with key ‘definition customers’ for microarchitecture and platform development, testing, and deployment. More details to come, especially as we move through Sapphire and Emerald Rapids during this year and next.

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  • mattj0707 - Tuesday, February 22, 2022 - link

    Intel 7 is definitely comparable to TSMC N7. Node names don't have any correlation to the actual features, performance or efficiency of the transistors themselves. We know for a fact that Intel 7 outperforms TSMC N7 in a few areas like transistor density, leakage, and drive current. So regardless if its called Intel 7 or 10 nm++++, it's performance is on par with TSMC's N7 so who cares what it's called at the end of the day. The performance is what matters, not the marketing name. Reply
  • duploxxx - Friday, February 18, 2022 - link

    The only reason there is no new or enhanced threadripper is due to OEM, they did not want to invest in it for there workstation lines and prefer to stay with the "financial funded intel" Xeon WS lines... Easy money for OEM and users are the ones that have no choice... its called abuse of power, the usual Intel stuff. So the threadripper market remained a niche and this is something difficult for AMD as they have so many EPYC delivery requests. Reply
  • Mike Bruzzone - Friday, February 18, 2022 - link

    duploxxx, Thread ripper over the last four years actually sold near equivalent Epyc; 13,676,597 unit and 14,269,999 respectively. Niche, well, E5 16xx product generations range 2.5 M to 5 M which is what TR displaced. E5/Scalable 2P workstation the components alone regardless of integration into to workstation my data only covers the components are 17x TR volumes. TR all generations has been a profitable niche for AMD. mb Reply
  • kwohlt - Sunday, February 20, 2022 - link

    Right, but Epyc is even more profitable than TR, and if AMD is struggling to meet demand on the more important Epyc chips, it doesn't make sense to divert capacity to make Zen 3 based TRs instead. Reply
  • Mike Bruzzone - Sunday, February 20, 2022 - link

    kwohit, I acknowledge agree AMD is going for commercial margin #1 Epyc #2 accelerator refocusing to GPU acceleration, Xilinx there too and deemphasizing AMD consumer GPU gaming when commercial [direct] customers write their own code but would not be surprised to see HP and Lenovo TR5K workstations showing up in secondary market 24 months from now and then there are 1P and 2P Epyc certainly workstation worthy at top of the frequency stack. Think about some Milan entering Genoa provided to HP and Lenovo as AMD MIlan contract completion award sustaining their own TR niche strongholds on direct customer sales is among the reasons I believe T5K does exist but not talked about. TR5K may also be needed as a March/April '22 AMD gross margin support parallel Rembrandt main deck dependent 3D volumes and acceptance. I have 15 M octa 3D and 1 M TR5K. mb Reply
  • Calin - Friday, February 18, 2022 - link

    "Ian: Which is a good thing."
    The datacenter customers do want their E-cores and P-cores.
    As such, they will buy (depending on their wants) 100,000 processors with E-cores only and 100,000 processors with P-cores.
    The "let's have some E-cores and some P-cores in the same chip" is not on their radar.
    Reply
  • schujj07 - Friday, February 18, 2022 - link

    He didn't say that datacenter customers don't want E-cores and P-cores. All he said was that it isn't wanted on the same CPU socket like the consumer space. Reply
  • drothgery - Friday, February 18, 2022 - link

    Largely an artifact of everyone going all-cloud all the time, I'd guess. A server owned and operated by a not very global business could use an E-core block to keep the lights on when it needs to be on but isn't very busy, but a cloud service provider is going to want to sell those unused cycles to someone else. Reply
  • Mike Bruzzone - Friday, February 18, 2022 - link

    I am fairly certain on production economic assessment TR 5K exists up to 1 M units, that HP and Lenovo sold workstation customer direct and will not be seen until they show up in the secondary market. This put the margin in AMD and OEM's pocket rather than the channel who likely would have inflated their own TR5K margin take. In both instances AMD avoids product inventoried and/or sitting on the shelf at Zen 3 run end production 'overpriced' while also reducing channel financial ability to purchase something else that moves in higher volume including from AMD.

    Ampere 3090ti is in the same position, sold direct. The Kingpin card is a commercial product in consumer disguise and requires the cooling infrastructure in place to integrate this subsystem into a cluster. Think white space limited high-density municipality located high frequency financial trading 24kW racks where the customer understands and has the cooling infrastructure in place to implement the 500W dGPU. Again in this instance, Nvidia with contract IDM take the margin and by keeping the card out of the channel and free from channel inflated pricing prevents whatever volume of 3090ti from sitting on the shelf, overpriced, and when they are sold the potential that in this example channel's inflated margin take will go to procurement of product other than Nvidia.

    AMD and Nvidia are both controlling how margin from the sale of their products comes back to them. And by keeping TR5K and 3090i out of the channel insure margin earned on those products goes back to them, and not Intel, who has benefited primarily for channel Ampere inflated margin take general funding Intel new procurements and not generally Nvidia new procurements.

    Mike Bruzzone, Camp Marketing
    Reply
  • Dr_b_ - Thursday, February 24, 2022 - link

    Agreed, where is HEDT. not enough PCIe lanes. Reply

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