Samsung Foundry on Wednesday said that it had started production of chips using its 7LPP manufacturing technology that uses extreme ultraviolet lithography (EUVL) for select layers. The new fabrication process will enable Samsung to significantly increase transistor density of chips while optimizing their power consumption. Furthermore, usage of EUVL allows Samsung to reduce the number of masks it requires for each chip and shrink its production cycle.

New Tech Brings in Big Gains

The maker of semiconductors says that 7LPP fabrication technology enables a 40% area reduction (at the same complexity) along with a 50% lower power consumption (at the same frequency and complexity) or a 20% higher performance (at the same power and complexity) when compared to 10LPE. As it appears, usage of extreme ultraviolet lithography for select layers enables Samsung Foundry to place more transistors inside its next-gen SoCs and reduce their power consumption, a very compelling proposition for mobile SoCs that will be used inside future flagship smartphones.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
vs 28LPP
vs 14LPE
vs 14LPP
vs 10LPE
vs 10LPE
Power 60% 40% 30% ~15% ? 50%
Performance 40% 27% >10% ~10% ? 20%
Area Reduction 50% 30% 30% none ? 40%

Samsung produces its 7LPP EUV chips at its Fab S3 in Hwaseong, South Korea. The company can process 1500 wafers a day on each of its ASML Twinscan NXE:3400B EUVL step and scan systems with a 280 W light source. Samsung does not say whether it uses pellicles that protect photomasks from degradation, but only indicates that usage of EUV enables it to cut the number of masks it requires for a chip by 20%. In addition, the company says that it had developed a proprietary EUV mask inspection tool to perform early defect detection and eliminate flaws early in the manufacturing cycle (which will likely have a positive effect on yields).

Samsung Foundry does not disclose the name of its customers that that first to adopt its 7LPP manufacturing technology, but only implies that the first chips to use it will be aimed at mobile and HPC applications. Usually, Samsung Electronics is the first customer of the semiconductor unit to adopt its leading-edge fabrication processes. Therefore, expect a 7nm SoC inside Samsung’s high-end smartphones due in 2019. Furthermore, Qualcomm will use Samsung’s 7LPP tech for its “Snapdragon 5G mobile chipsets”.

“With the introduction of its EUV process node, Samsung has led a quiet revolution in the semiconductor industry,” — said Charlie Bae, executive vice president of foundry sales and marketing team at Samsung Electronics. “This fundamental shift in how wafers are manufactured gives our customers the opportunity to significantly improve their products’ time to market with superior throughput, reduced layers, and better yields. We’re confident that 7LPP will be an optimal choice not only for mobile and HPC, but also for a wide range of cutting-edge applications.”

Advanced IP and Packaging: Ready for 7LPP

Samsung’s 7LPP manufacturing technology offers impressive advantages over the company’s 10LPE specifically for mobile SoCs. Meanwhile, in a bid to make the process attractive to a broad range of potential customers, the foundry offers a comprehensive set of design-enablement tools, interface IP (controllers and PHY), reference flows, and advanced packaging solutions. The final PDK is months away, but many customers may start development of their 7LPP SoCs even with existing set of solutions.

At this point 7LPP is supported by numerous Samsung Advanced Foundry Ecosystem (SAFE) partners, including Ansys, Arm, Cadence, Mentor, SEMCO, Synopsys, and VeriSilicon. Among other things, Samsung and the said companies offer such interface IP solutions HBM2/2E, GDDR6, DDR5, USB 3.1, PCIe 5.0, and 112G SerDes. Therefore, developers of chips of SoCs due in 2021 and onwards, which will rely on PCIe Gen 5 and DDR5, can start designing their chips right now.

As for packaging, chips made using 7LPP EUV technology can be coupled with 2.5D silicon interposer (if HBM2/2E memory is used) as well as Samsung’s embedded passive substrates.

Expanding EUV Capacity

As noted above, Samsung installed EUV production tools at its Fab S3, which still has plenty of DUV (deep ultraviolet) equipment. As EUVL is used only for select layers of 7LPP chips, the relatively limited number of Twinscan NXE:3400B scanners is hardly a problem, but when Samsung’s process technologies will require EUV for more layers, it may need to expand its EUV capacities.

As reported in September, a major increase of EUV lithography usage by Samsung Foundry will happen after it builds another production line in Hwaseong, which was architected for the EUV tools from the start. The fab is set to cost 6 trillion Korean Won ($4.615 billion), it is expected to be completed in 2019, and start HVM in 2020.

33 Years in Development

The launch of commercial production of chips using extreme ultraviolet lithography is a culmination of work by the whole semiconductor industry that began in 1985. Ultimately, EUVL is expected to reduce usage of multi-patterning when producing complex elements of a chip and therefore simplify design process, improve yields, and shrink cycle times (or rather not make them longer in the foreseeable future).

Meanwhile, it was extremely challenging to bring EUV from drawing boards to actual fabs because the technology is extremely complex. It needs all-new step-and-scan systems outfitted with all-new light source, new chemicals, new mask infrastructure, and numerous other components that took years to develop. To learn more about EUV lithography, please check our article from 2016.

Related Reading:

Source: Samsung
Image Source: PC Watch

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  • Amandtec - Wednesday, October 17, 2018 - link

    To be fair : GF and Intel have found 7nm extremely challanging. Samsung it doing pretty well here. TSMC is flying.
  • Gondalf - Thursday, October 18, 2018 - link

    Are you sure "pretty well" ? Your statement is vague. What is "pretty well" ?
    A bunch of wafers at 50% yields (no pellicles at all because not available not even in upcoming years) done only because Samsung "need" to manufacture the next phone SOC instead of Apple will destroy the high end market?
    If true your definition of "pretty well" do not fit to Intel or GloFo business structure.

    Ps. no mention to yields on this article, only marketing fluff
  • jospoortvliet - Saturday, October 20, 2018 - link

    They are producing... slow, bad or expensive - something beats nothing ;-)
  • bobhumplick - Sunday, October 28, 2018 - link

    cpus running from from 65 watts to a few hundred are a whole different story. if all intel had to do was make a 1 watt soc they would have had it out a couple years ago
  • t_oven - Sunday, October 21, 2018 - link

    Apple always hurt SS one way or another. Directly SS need to compete with A12 7nm, also Apple put a lot of money into TSMC allow them to develop 7nm so quickly and benefit another SS competitor, name Qualcomm Snapdragon.
  • neblogai - Wednesday, October 17, 2018 - link

    Regarding the second paragraph: does it offer a 40% area reduction, or '40% more transistors' in the same area?
  • foobaz - Wednesday, October 17, 2018 - link

    don't those work out to be the same thing?
  • neblogai - Wednesday, October 17, 2018 - link

    Well, 40% area reduction means 66.6% more transistors per area.
  • ZolaIII - Thursday, October 18, 2018 - link

    It means same as written approximately 40% area reduction for same complexity for all included logical blocks including complex one's as the transistor. It's probably even 2x for transistor but much less then 40% for SRAM.
  • ajp_anton - Thursday, October 18, 2018 - link

    -40% means 0.6x size
    0.6x size means 1.67x more (1/0.6)
    1.67x more means +67%

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